In the world of flip-flops, the Clocked JK Flip Flop stands out with its outstanding features, such as all usable input states and the ability to be modified to imitate other flip-flops like SR, T, and D. This makes the JK Flip Flop a little better than the others. It's often called a universal flip-flop.
The JK flip-flop's main advantage is its ability to handle all possible input combinations without any issues. This includes a useful toggle operation that makes it great for building counters and frequency dividers. You'll find JK flip-flops in many everyday electronics, from the timing circuits in microprocessors to LED flashers in gadgets. They're commonly used in digital counters, frequency synthesisers, and control systems for various applications.
In this article, we'll walk through how the Clocked JK Flip Flop works, explore the clocked JK Flip Flop truth table and some practical uses that make it such a popular choice in digital circuit design.
Clocked JK FlipFlop
This Clocked JK Flip-Flop can be referred to by multiple names like JK Flip-Flop, Clocked JK Latch, or Clocked JK Flip-Flop. These variations mostly come from naming confusion. In general, a latch is a combinational circuit that requires no clock pulse, whereas a flip-flop, on the other hand, needs a clock to function. That’s why the term “Clocked” is often added, making it a Clocked JK Flip-Flop.
This Clocked JK Flip-Flop has two inputs, J and K, which function similarly to the Set and Reset inputs in an SR flip-flop, but with a smart upgrade. When both J and K are held HIGH, instead of entering an invalid or unstable state (as seen in the SR flip-flop), the JK flip-flop simply toggles its output with each edge-trigger pulse.
For reference, you can see the basic symbol and the Clocked JK flip flop truth table below.
Here, you can easily understand the Clocked JK Flip Flop by observing the truth table. Below, you can see a brief explanation of the working of the Clocked JK Flip Flop.
| J = 0, K = 0 ("00") |
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| J = 0, K = 1 ("01") |
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| J = 1, K = 0 ("10") |
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| J = 1, K = 1 ("11") |
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Clock is stable (no edge), J or K can be anything |
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Now you should have some idea of how the JK Flip Flop works. Next, let’s look at the Clocked JK Flip Flop circuit diagram.
Advantages of Clocked JK Flip-Flops
⇒ No Invalid States : Unlike SR flip-flops, JK flip-flops eliminate forbidden input combinations completely.
⇒ Toggle Functionality : Built-in toggle capability when both J and K inputs are high.
⇒ Universal Flip-Flop : Can be configured to emulate SR, D, and T flip-flops.
⇒ Edge-Triggered Operation : Synchronous operation with clock edges prevents timing race conditions.
⇒ Memory Capability : Holds previous state when both inputs are low effectively.
⇒ Versatile Input Control : Four distinct input combinations provide complete output state control.
⇒ Clock Synchronization : All state changes occur synchronously with clock signal transitions.
Clocked JK Flip Flop Logic Diagram
In real time, there are many simple ways to achieve the JK Flip Flop, such as a Clocked JK Flip-Flop using NAND gates, a Clocked JK Flip Flop using NOR gates, or a Clocked JK Flip-Flop using a dedicated Integrated Circuit chip like the 74LS76.
Let’s go through all three in simple terms.
1. Clocked JK Flip Flop using NAND Gate
To create a JK Flip Flop using NAND gates, we need a total of six 2-input NAND gates. The JK Flip Flop circuit diagram looks like this:
In some places, you might also see a simplified diagram that uses 3-input NAND gates. That works too, but based on my experience with simulation, the 2-input NAND configuration works better than the 3-input version. You can read more about these details in one of our articles, Flip-Flop in Digital Electronics: Types, Truth Table, Logic Circuit and Practical Demonstration, which explains all types of flip-flops.
The working is the same as a regular JK Flip-Flop.
- When J = 0 and K = 0, the flip-flop does nothing on a clock edge. It simply holds on to its previous state. This is called the memory or no-change condition.
- When J = 0 and K = 1, the flip-flop resets on the clock edge. The output Q becomes 0, and Q̅ becomes 1.
- When J = 1 and K = 0, the flip-flop sets on the clock edge. The output Q becomes 1, and Q̅ becomes 0.
- When J = 1 and K = 1, the flip-flop toggles its output every clock edge. If Q was 0, it becomes 1, and if Q was 1, it becomes 0. This toggle action is commonly used in JK Flip Flop counters.
- If the clock is stable (not changing), the outputs remain the same no matter what J and K are. A JK flip-flop only changes state when the clock edge occurs.
2.Clocked JK Flip Flop using NOR Gate
When creating a JK Flip Flop using NOR gate, not all NAND gates are replaced with NOR gates. Instead, only the two NAND gates at the output (Q and Q̅) are replaced with NOR gates, while the input stage remains with NAND gates. However, the NAND gate versions are more commonly used and preferred.
Above, you can see the logic diagram of the Clocked JK Flip Flop using NOR gate. It follows the same logic as the general JK Flip-Flop, so I didn’t repeat the explanation here. You can refer to the above section for better understanding.
3.Clocked JK Flip-Flop using direct ICs
There are several ICs that come with a Clocked JK Flip Flop embedded in them.
An example of such an integrated circuit (IC) is the 7476 IC. This chip contains two separate positive-edge-triggered JK flip-flops with individual J, K, clock, preset, and clear inputs. It’s a common choice for digital design projects where JK flip-flop behavior is needed.
Other commonly used JK flip-flop ICs are:
| 7476 IC: | Contains two JK flip-flops in one package. Each flip-flop has its own J, K, clock, preset, and clear input, making it versatile for toggling, setting, resetting, and memory operations. |
| 74LS76: | Similar to the 7476 but from the low-power Schottky (LS) TTL family. Features dual JK flip-flops with set and clear functions, commonly used in TTL logic circuits. |
| CD4027: | CMOS implementation of two JK master-slave flip-flops. Each flip-flop operates synchronously, making it useful for counters and registers in low-power or mixed-signal designs. |
| 74LS112: | Another TTL-based chip with dual JK flip-flops, each featuring preset (set to 1) and clear (reset to 0) controls for more direct state management. |
Applications of Clocked JK Flip-Flops
All these ICs provide reliable JK flip-flop logic, making them useful for applications like:
1. Digital Counters : Binary counting circuits using toggle mode for sequential operations.
2. Frequency Division Circuits : Clock signal frequency division by factors of two repeatedly.
3. Shift Registers : Serial and parallel data shifting for communication and storage.
4. Memory Storage Systems : Static RAM cells and buffer registers for data retention.
Common Types of flip-flops
There are several types of flip-flops in digital electronics, each designed to perform specific functions in storing and controlling data. While they all operate on the basic principle of bistable states, their input configurations and applications vary. The most common types are:
SR Flip-Flop with NAND Gates: Circuit, Truth Table and Working
Understand the SR flip-flop built with NAND gates, including its logic circuit, truth table, and working using IC SN74HC00N.
JK Flip-Flop: Circuit, Truth Table and Working
Explore the JK flip-flop, its truth table, circuit logic using NAND gates, and practical implementation with the MC74HC73A dual flip-flop IC.
D Type Flip-Flop: Circuit, Truth Table and Working
Learn how a D-type flip-flop works, including its clock-dependent behaviour, truth table, and logic implementation with NAND gates or the HEF4013BP dual flip-flop IC.
T Flip-Flop: Circuit, Truth Table and Working
Explore the T (Toggle) flip-flop, its logic circuit using NAND gates, truth table, and its behaviour when paired with the MC74HC73A dual JK flip-flop IC.
