JK Flip-Flop: Circuit, Truth Table and Working

digital

ByArvind Ragupathy 2

JK Flip-Flop: Circuit, Truth Table and Working

The term digital in electronics represents the data generation, processing or storing in the form of two states. The two states can be represented as HIGH or LOW, positive or non-positive, set or reset which is ultimately binary. The high is 1 and low is 0 and hence the digital technology is expressed as series of 0’s and 1’s. An example is 011010 in which each term represents an individual state. Thus, this latching process in hardware is done using certain components like latch or Flip-flop, Multiplexer, Demultiplexer, Encoders, Decoders and etc collectively called as Sequential logic circuits.

So, we are going to discuss about the Flip-flops also called as latches. The latches can also be understood as Bistable Multivibrator as two stable states. Generally, these latch circuits can be either active-high or active-low and they can be triggered by HIGH or LOW signals respectively.

The common types of flip-flops are,

  1. RS Flip-flop (RESET-SET)
  2. D Flip-flop (Data)
  3. JK Flip-flop (Jack-Kilby)
  4. T Flip-flop (Toggle)

Out of the above types only JK and D flip-flops are available in the integrated IC form and also used widely in most of the applications. Here in this article we will discuss about JK Flip Flop.

 

JK Flip-flop:

The name JK flip-flop is termed from the inventor Jack Kilby from texas instruments. Due to its versatility they are available as IC packages. The major applications of JK flip-flop are Shift registers, storage registers, counters and control circuits. Inspite of the simple wiring of D type flip-flop, JK flip-flop has a toggling nature. This has been an added advantage. Hence they are mostly used in counters and PWM generation, etc. Here we are using NAND gates for demonstrating the JK flip flop

Whenever the clock signal is LOW, the input is never going to affect the output state. The clock has to be high for the inputs to get active. Thus, JK flip-flop is a controlled Bi-stable latch where the clock signal is the control signal. Thus, the output has two stable states based on the inputs which have been discussed below.

JK flip-flop symbol

 

Truth table of JK Flip Flop:

Clock

INPUT

OUTPUT

RESET

J

K

Q

Q’

X

LOW

X

X

0

1

HIGH

HIGH

0

0

No Change

HIGH

HIGH

0

1

0

1

HIGH

HIGH

1

0

1

0

HIGH

HIGH

1

1

Toggle

LOW

HIGH

X

X

No Change

HIGH

HIGH

X

X

No Change

HIGH

HIGH

X

X

No Change

The J (Jack) and K (Kilby) are the input states for the JK flip-flop. The Q and Q’ represents the output states of the flip-flop. According to the table, based on the inputs, the output changes its state. But, the important thing to consider is all these can occur only in the presence of the clock signal. This, works like SR flip-flop for the complimentary inputs and the advantage is that this has toggling function.

 

Representation of JK Flip-Flop using Logic Gates:

Representation of JK Flip-Flop using NAND Gates

 

JK flip-flop-with NAND gates example truth table

Thus, comparing the three input and two input NAND gate truth table and applying the inputs as given in JK flip-flop truth table the output can be analysed. Analysing the above assembly as a two stage structure considering previous state (Q’) to be 0

 

When J = 1, K = 0 and CLOCK = HIGH

 

D-flip-flop--with-NAND-gates-example

Output: Q = 1, Q’ = 0. Working is correct.

 

RESET:

The RESET pin has to be active HIGH. All the pins will become inactive upon LOW at RESET pin. Hence, this pin always pulled up and can be pulled down only when needed.

 

IC Package:                                                                                 

JK flip-flop ic MC74HC73A pin diagram

Q

True Output

Q’

Compliment Output

CLOCK

Clock Input

J

Data input 1

K

Data input 2

RESET

Direct RESET (Low activated)

GND

Ground

VCC

Supply voltage

The IC used is MC74HC73A (Dual JK-type flip-flop with RESET). It is a 14 pin package which contains 2 individual JK flip-flop inside. Above is the pin diagram and the corresponding description of the pins.

 

Components Required:

  1. IC MC74HC73A (Dual JK flip-flop) – 1No.
  2. LM7805 – 1No.
  3. Tactile Switch – 4No.
  4. 9V battery – 1No.
  5. LED (Green – 1; Red – 1)
  6. Resistors (1kὨ - 4; 220kὨ -2)
  7. Breadboard
  8. Connecting wires

 

JK Flip-flop Circuit diagram and Explanation:

JK flip-flop circuit diagram with IC MC74HC73A

The IC power source VDD ranges from 0 to +7V and the data is available in the datasheet. Below snapshot shows it. Also we have used LED at output, the source has been limited to 5V to control the supply voltage and DC output voltage.

JK flip-flop ic MC74HC73A datasheet

We have used a LM7805 regulator to limit the LED voltage.

 

Practical Demonstration and Working of JK Flip-Flop:

The buttons J(Data1), K(Data2), R(Reset), CLK(Clock) are the inputs for the JK flip-flop. The two LEDs Q and Q’ represents the output states of the flip-flop. The 9V battery acts as the input to the voltage regulator LM7805. Hence, the regulated 5V output is used as the Vcc and pin supply to the IC. Thus, for different input at D the corresponding output can be seen through LED Q and Q’.

The pins J, K, CLK are normally pulled down and pin R is pulled up. Hence, default input state will be LOW across all the pins except R which is state of normal operation. Thus, the initial state according to the truth table is as shown above. Q=1, Q’=0. The LEDs used are current limited using 220Ohm resistor.

JK flip-flop working and circuit

Note: Since the CLOCK is HIGH to LOW edge triggered, both input button should be pressed and hold till releasing the CLOCK button.

Below we have described the various states of JK Flip-Flop using a Breadboard circuit with IC MC74HC73A. A demonstration Video is also given below:

 

State 1:

Clock– HIGH ; J – 0 ; K – 1 ; R – 1 ; Q – 0 ; Q’ – 1

For the State 1 inputs the RED led glows indicating the Q’ to be HIGH and GREEN led shows Q to be LOW. The working can be verified with the truth table.

Note: R is already Pulled up so no need to press the button to make it 1.

JK-flip-flop-working-state-one-Clock-HIGH--J-0,K-1,R-1

 

State 2: Clock– HIGH ; J – 1 ; K – 0 ; R – 1 ; Q – 1 ; Q’ – 0

For the State 2 inputs the GREEN led glows indicating the Q to be HIGH and RED led shows Q’ to be LOW. The same can be verified with the truth table.

JK-flip-flop-working-state-one-Clock-HIGH--J-1,K-0,R-1

 

State 3: Clock– HIGH ; J – 1 ; K – 1 ; R – 1 ; Q/Q’ – Toggle between two states

For the State 3 inputs the RED and GREEN leds glows alternatively for each clock pulse (HIGH to LOW edge) indicating the toggling action. The output toggle from the previous state to another state and this process continues for each clock pulse.

For first clock pulse with J=K=1

JK flip-flop working state three Clock-HIGH--J-1,K-1,R-1

 

For second clock pulse with J=K=1

JK flip-flop working state one Clock HIGH--J-1,K-1,R-1

 

State 4: Clock– LOW ; J – 0 ; K – 0 ; R – 0 ; Q – 0 ; Q’ – 1

Note: R is already Pulled up so we need to press the button to make it 0.

The State 4 output shows that the input changes does not affect under this state. The output RED led glows indicating the Q’ to be HIGH and GREEN led shows Q to be LOW. This state is stable and stays there until the next clock and input is applied with RESET as HIGH pulse.

JK flip flop working state Clock 0--J-0, K-0, R-0

 

State 5: The remaining states are No change states during which the output will similar to previous output state. The changes do not affect the output states, you can verify with the Truth Table above.

 

The complete working and all the states are also demonstrated in the Video below.

Video

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Comments

  • Amir Abbass Zahir Mobarhan's picture
    Amir Abbass Zah...
    Sep 30, 2017

    Hello

    clock must be edge trigger.relation between jk flip flop and d type & t type flip flops.

    is the truth table correct.output must associates to previous output.

    if my problems are incorrect,please tell me.

  • Arvind Ragupathy's picture
    Arvind Ragupathy
    Oct 02, 2017

    Hi,
    Here the clock is falling edge triggered (HIGH to LOW edge).
    The truth tables are correct from practical point of view.
    Yes, the output state will be based on previous state where the NO CHANGE
    output makes no difference but the TOGGLE output makes the difference and
    it could be seen in above demonstration.

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