Cyient Semiconductors and MIPS have announced a strategic collaboration to develop ASIC and ASSP solutions using MIPS Atlas processor IP. They aim to deliver domain-optimized solutions for automotive, industrial, and data center applications. The companies believe that their collaboration will allow for the development of next-gen semiconductor solutions that use embedded intelligence, real-time performance, and advanced power architecture together, tailored for a more connected, efficient, and scalable future.
The focus is on real-time and safety-critical applications, power delivery systems, and compute efficiency for demanding environments. The combination of Cyient’s analog-mixed signal design prowess and MIPS Atlas CPUs will be integrated primarily into motor control and data center power delivery platforms. The collaboration is based on the open RISC-V instruction set, avoiding dependencies (vendor lock-ins).
Cyient supports the entire chip lifecycle from architecture to production and works with semiconductor firms, OEMs, Tier-1s, foundries, and OSATs. Suman Narayan, CEO of Cyient Semiconductors, said, “As compute systems scale from cloud to the edge, intelligent power delivery is emerging as a key enabler of performance and efficiency”.
MIPS is a 40-year-old company that focuses on real-time computing for autonomous platforms. It offers M8500 microcontrollers for power efficiency and motor control. According to Sameer Wasson, CEO of MIPS, “The problem of power efficiency and motor control are both real-time compute workloads for which MIPS M8500 microcontrollers are the optimal choice”.
