Toshiba Develops Ultra-low-power Analog AI Accelerator Chip for Embedded Systems

Analog AI Accelerator Chip will accelerate the origination of AI technologies into embedded devices which have been difficult until now.


Toshiba has invented an ultra-low-power analog AI accelerator chip for an embedded system. This technology performs the multiply-accumulate operation, which reports for the majority of neural network operation. It uses the only one-eighth power of the current digital circuit. The chip introduces AI technologies into an embedded system that runs on battery power, energy harvesting, or remote wireless power.

AI technology’s attention is to cover not only image processing but all the fields like industrial machinery, medicine and healthcare, mobile consumer devices, and Internet of Things devices.


Interaction Problem between AI and Embedded System

In cloud-based AI, sensors and cloud-based neural network required high speed wired and wireless communication to analyze the large amounts of sensor data from embedded devices. Sometimes the speed of communication creates a barrier to the introduction of AI. The hardware cost and power consumption are also the problems for the introduction of AI into embedded devices.


Features of Analog AI Accelerator Chip

The chip uses a novel phase-domain analog circuit technology. Toshiba’s technology uses the phase domain of an oscillation circuit for multiply-accumulate operation, which is not been used normally. Toshiba’s technology uses the oscillation time and frequency by controlling it dynamically. So, it can able to process multiplication, addition, and memory operations that are conventionally processed by individual digital circuits. Therefore, it helps in reducing power consumption to one-eighth of digital circuits with the same area.

Application of the Ai accelerator chip to inference processing in a neural network for image recognition and anomaly detection is successfully demonstrated by Toshiba.

Product sum operation circuit benchmarks


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