LoRa Corecell Reference Design for Full-Duplex Gateway Applications to Improve LoRaWAN network Communication Efficiency


ByRajni Setia 0

SX1302CFD915GW1-H LoRa Corecell Reference Design

The new LoRa Corecell reference design, SX1302CFD915GW1-H from Semtech Corporation helps improve LoRaWAN network communication efficiency and reduces time and cost of operational management of end devices. Released specifically for Full-Duplex Gateway Application in the U.S. 902 - 928MHz ISM band, it enables LoRaWAN gateways to simultaneously receive and transmit data while expanding the reach and connectivity of LoRa.

From smart metering, smart building, and smart factory, the new turnkey gateway solution enables the expansion of network capacity for various outdoor and indoor applications. Besides, the reference design enables network owners to increase network capacity while deploying fewer gateways, providing cost savings to end customers when compared to cellular alternatives.

The SX1302CFD915GW1-H full-duplex LoRa Corecell reference design improves LoRaWAN protocol message response time for applications requiring fast acknowledgment from the gateway, thereby enabling Firmware Update Over-The-Air (FUOTA) while processing uplink traffic and reduces the time and cost of operational management of end devices. In addition to simultaneous transmission of data, the full-duplex design helps in lengthening the downlink window to enable gateways to send more data to end devices and removing the latency experienced with half-duplex gateways.

Features of LoRa Corecell Reference Design for Full-Duplex Gateway Applications

  • Full duplex mode

  • 10x power reduction compared to legacy products

  • Transmit power (US915) up to +27dBm

  • Receive sensitivity (US915) down to -140.8dBm at SF12, 125kHz BW, -124.2dBm at SF7, 125kHz BW and -118.9dBm at SF5, 125kHz BW

  • 8 frequency channels

  • 16 125kHz BW LoRa demodulators

  • One high speed 125/250/500kHz multi-bandwidth LoRa demodulator

  • (G)FSK demodulator

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