Diodes Incorporated has released a PCIe GEN3 packet switch, PI7C9X3G808GP that delivers high-performance parameters mandated by modern data center, cloud computing, network-attached storage (NAS), and telecom infrastructure implementations. This PCIe packet switch supports 8 lanes of GEN3 SERDES in flexible 2-port, 3-port, 4-port, 5-port, and 8-port configurations.
The PI7C9X3G808GP switch comes in a high-performance, flip-chip package with 196-ball BGA format and measures 15 x 15mm. The architecture of this PCIe packet switch is such that it enables the flexible port configuration by allocating variable lane widths for each port. There are multiple port/lane width combinations available along with cross-domain, end-point (CDEP) arrangements. The PI7C9X3G808GP supports fan-out and dual-host connectivity because of its CDEP capabilities.
There is a built-in PCIe 3.0 clock buffer that allows for a reduction in the overall component count and helps to curb BOM costs. This integrated buffer is unique to the industry because of its low-power operation. Common, separate reference no spread (SRNS), and separate reference independent spread (SRIS) are the three different reference clock options that can be used. Besides, the switch has multiple direct memory access (DMA) channels that have been embedded into the switch for making communication between host or hosts and connected end-points as efficient as possible.
Error-handling, advanced error reporting, and end-to-end data protection with error correction and key functionality in terms of reliability, availability, and serviceability (RAS) are the notable features of this PCIe GEN3 packet switch. The switch has hot-pluggable ports that are empty and kept in a low-power state until required. While under full-load conditions and 80°C junction temperature, the PI7C9X3G808GP will draw only 2.9W of power.