New Smart High Level Synthesis (HLS) Tool Suite from Microchip enables C++ algorithms to be directly translated to FPGA-optimized Register Transfer Level (RTL) code thereby enhancing productivity and providing ease of design. Based on the open-source Eclipse integrated development environment, the SmartHLS design suite uses C++ software code to generate an HDL IP component for integration into Microchip’s Libero SmartDesign projects. This helps in reducing development time through a multi-threading Application Programming Interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism.
As told by the company officials, the Smart High Level Synthesis (HLS) Tool Suite along with Microchip’s VectorBlox Neural Network Software Development Kit will significantly improve designers’ productivity in creating cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control and industrial automation using FPGA-based hardware accelerators.
The tool requires up to 10 times fewer lines of code making resultant code easier to read, understand, test, debug and verify. Moreover, it simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to be used with PolarFire FPGAs and FPGA SoCs. SmartHLS v2021.2 tool can be used either individually as stand-alone software or in combination with the recently released Libero SoC V2021.2 design suite.