The Renesas Electronics Corporation has introduced the new high speed, low power DDR5 data buffer for data center, server, and high-performance workstation applications. The new JEDEC compliant DDR5 data buffer 5DB0148 can lower the latency for load reduced dual inline memory modules (LRDIMMs) in the new class applications like real-time analytics, machine learning, HPC, AI, and other memory and bandwidth-hungry applications.
The first generation DDR5 LRDIMMs enable a bandwidth increase of more than 35% over DDR4 LRDIMMs operating at 3200MT/s. The new data buffer maximizes channel eye-opening for systems that are heavily loaded through a combination of capacitive load reduction, data alignment, and signal recovery techniques. Hence the motherboards with a large number of memory channels and slots and complex routing topologies can run at maximum speed even when fully populated with high-density memory.
The new improvements in the DDR5 modules allow lower power supply voltages (1.1V vs 1.2V in DDR4), on DIMM voltage regulation. With the help of the SPD Hub and modern control bust communication such as I3C, the new device can implement advanced control plane architectures.