Decoupling capacitors for schematic design query

CarterJohn11's picture

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Joined: Dec 17, 2019

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Decoupling capacitors for schematic design query
December 17, 2019 - 1:15am

I'm just upgrading the SDRAM on my build from 4GB DDR3 SDRAM to 4GB LPDDR4 SDRAM & currently following the Nanopi M4V2's schematic detailing the decoupling capacitors to connect to the relevant pins.

After setting everything up, I noticed on the schematic drawing that was 1* VCC_DDR & 3* VCC_DDRC connections for the SDRAM chip; however when looking at the respective decoupling capacitors there is 2* VCC_DDR & 2* VCC_DDRC connections. So I'm curious as to whether they in fact messed up the label on 1 of the VCC_DDRC's and that it is actually meant to be an VCC_DDR or not?

Also how do I distinguish which decoupling capacitor components I should connect to which pin or do I simply connect all of the DDRC's to the 2* VCC_DDRC decouplers and vice versa for the single VCC_DDR to the 2* VCC_DDR decoouplers?

Bradyen's picture

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Joined: Aug 14, 2018

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hey what are you building with your nano pi anyway? 

decoupling capacitors can  be identified if the other end is connected to ground. also 2* VCC_DDR & 2* VCC_DDRC looks like a printing mistake to me not sure though. can you share the link to the shematic you are talking about!

Sourav Gupta's picture

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Joined: Feb 12, 2018

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Kindly share the schematic for reference.