The objective of this project is to implement, in VHDL, a Finite State Machine, using the main clock of the Digilent Board to drive the state machine. The finite state machine will control a vending machine to dispense soda cans that are worth 50¢. Since this project will require several modules, consider using a mixed schematic/VHDL design, where you can use a schematic as the top level module, and have each sub-module defined in VHDL.
The vending machine has three inputs:
QUARTER: a signal that goes high and then low when a quarter has been deposited
CLOCK: a clock that will drive the FSM
RESET: a signal that will reset the FSM to its initial state
The vending machine has two outputs:
COUNT: a signal that goes high when a single quarter has been accepted. This signal should remain high for one clock cycle.
DISPENSE: a signal that goes high when the soda has been dispensed
Part I
Create a clock divider module to divide the master clock (at 50MHz) to a 1Hz clock. You may also need to create a switch debouncer for the QUARTER input to avoid confusing the FSM.
Part 2
Create your state diagram that you will use to implement the FSM VHDL module. The vending machine behaves as follows:
- If the RESET input is asserted, the FSM will go to the initialization state (S_init) immediately. All of the outputs should be zero in this state.
- From the initialization state S_init, the FSM will unconditionally go to the wait state (S_wait)
- From the wait state S_wait, the FSM waits for the QUARTER switch to be activated.
- If QUARTER is asserted, the FSM goes to state S_Q1. In this state, the COUNT output is set to 1, indicating that a quarter has been accepted. The FSM will stay in this state until the QUARTER input is de-asserted. When this occurs, the FSM goes to state S_QW1, then unconditionally to state S_QW2 and the COUNT output is set to 0. The FSM waits for the QUARTER switch to be activated.
- If QUARTER is asserted while the FSM is in S_QW2, then the state machine goes to state S_Q2. In this state, the COUNT output is again set to 1. The FSM will stay in this state until the QUARTER input is de-asserted. When this occurs, the FSM goes to S_QW3, and then unconditionally to state S_dispense, the COUNT output is set to 0, and the DISPENSE output is set to 1.
- From state S_dispense, the FSM unconditionally goes to state S_init.
Your VHDL MUST have two process: a next-state process to determine the change of states, and a output_logic process, to determine the outputs.
